Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC Cluster


Commodity SoCs with hybrid architectures that combine CPUs with programmable FPGA fabric such as the Xilinx Zynq SoC have become a competitive energy-efficient platform for addressing irregular parallelism in graph problems. In this paper, we prototype a 32-node cluster composed from these Zynq SoC chips to accelerate communication-bound sparse graph… (More)
DOI: 10.1109/FCCM.2015.37


14 Figures and Tables