Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development

@article{Spiesshoefer2004ZaxisIU,
  title={Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development},
  author={S. Spiesshoefer and L. W. Schaper and S. Burkett and G. Vangara and Zahidul Rahman and Parthiban Arunasalam},
  journal={2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)},
  year={2004},
  volume={1},
  pages={466-471 Vol.1}
}
A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced MCMs. This technology overcomes the RC delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and 3-D stacking… CONTINUE READING
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