Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

  title={Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND},
  author={Teng-Hao Elton Yeh and Wei-Chen Chen and Tzu-Hsuan Bruce Hsu and Pei-ying Du and Chih-Chang Hsieh and Hang-Ting Lue and Yen-Hao Shih and Ya-Chin King and Chih-Yuan Lu},
  journal={IEEE Transactions on Electron Devices},
In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (Vt) shift due to two unique mechanisms. The first mechanism is the fringing field of the programmed charges (Z-interference), whereas the second one is the degraded inhibited potential affected by the… CONTINUE READING


Publications citing this paper.


Publications referenced by this paper.
Showing 1-10 of 15 references

Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) • 2014
View 3 Excerpts

Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage

C.-C. Hsieh
Proc. Symp. VLSI Technol., Jun. 2013, pp. T156–T157. • 2013
View 1 Excerpt

Scaling directions for 2D and 3D NAND cells

2012 International Electron Devices Meeting • 2012
View 1 Excerpt

A Novel 3D Cell Array Architecture for Terra-Bit NAND Flash Memory

2011 3rd IEEE International Memory Workshop (IMW) • 2011
View 1 Excerpt

Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash

2011 International Reliability Physics Symposium • 2011
View 1 Excerpt

Similar Papers

Loading similar papers…