Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

@article{Yeh2016ZInterferenceAZ,
  title={Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND},
  author={Teng-Hao Elton Yeh and Wei-Chen Chen and Tzu-Hsuan Bruce Hsu and Pei-ying Du and Chih-Chang Hsieh and Hang-Ting Lue and Yen-Hao Shih and Ya-Chin King and Chih-Yuan Lu},
  journal={IEEE Transactions on Electron Devices},
  year={2016},
  volume={63},
  pages={1047-1053}
}
In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (Vt) shift due to two unique mechanisms. The first mechanism is the fringing field of the programmed charges (Z-interference), whereas the second one is the degraded inhibited potential affected by the… CONTINUE READING

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