Yield and speed optimization of a latch-type voltage sense amplifier

@article{Wicht2004YieldAS,
  title={Yield and speed optimization of a latch-type voltage sense amplifier},
  author={Bernhard Wicht and Th. Nirschl and Doris Schmitt-Landsiedel},
  journal={IEEE Journal of Solid-State Circuits},
  year={2004},
  volume={39},
  pages={1148-1158}
}

• Bernhard Wicht, Th. Nirschl, Doris Schmitt-Landsiedel
• Published in IEEE Journal of Solid-State Circuits 2004
• DOI:10.1109/JSSC.2004.829399

A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD… CONTINUE READING

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