Yield and reliability of 3DIC technology for advanced 28nm node and beyond

@article{Yang2011YieldAR,
  title={Yield and reliability of 3DIC technology for advanced 28nm node and beyond},
  author={K. F. Yang and T. J. Wu and W. C. Chiou and M. F. Chen and Y. C. Lin and F. W. Tsai and C. C. Hsieh and C. H. Chang and W. M. Wu and Y. H. Chen and T. Y. Chen and H. Wang and I. C. Lin and S. B. Jan and R. D. Wang and Y C Lu and Y. C. Shih and H. A. Teng and C. S. Tsai and M. N. Chang and Kim Chen and S. Y. Hou and S. P. Jeng and C. H. Yu},
  journal={2011 Symposium on VLSI Technology - Digest of Technical Papers},
  year={2011},
  pages={140-141}
}
A stacked three-dimension integrated circuit (3D-IC) of 28nm chips was demonstrated. Key enabling technologies such as through silicon via (TSV) formation, wafer thinning, redistribution layer (RDL), micro bump and joint were developed for chip stacking and interconnect functions evaluation. The excellent performances of 3D-IC yield and reliability characteristics are key milestones in promising manufacturability of 3D-IC by silicon foundry technology.