Yield analysis of partial defect tolerant bit-plane array

@article{Ciric2010YieldAO,
  title={Yield analysis of partial defect tolerant bit-plane array},
  author={Vladimir Ciric and Aleksandar M. Cvetkovic and Ivan Milentijevic},
  journal={Computers & Mathematics with Applications},
  year={2010},
  volume={59},
  pages={98-107}
}
Silicon complexity places long-stand paradigms at risk. Key concerns include increasing process variations, defect rates, infant mortality rates, and susceptibility to internal and external noises. These trends are likely to decrease functional yield. Fabrication of die with 100%working transistors and interconnections becomes prohibitively expensive. This paper examines the size and the position of the candidate part of the architecture for defect tolerance application, for the given topology… CONTINUE READING