Xar-trek: run-time execution migration among FPGAs and heterogeneous-ISA CPUs

@article{Horta2021XartrekRE,
  title={Xar-trek: run-time execution migration among FPGAs and heterogeneous-ISA CPUs},
  author={Edson Lemos Horta and Ho-Ren Chuang and Naarayanan Rao VSathish and Cesar J. Philippidis and Antonio Barbalace and Pierre Olivier and Binoy Ravindran},
  journal={Proceedings of the 22nd International Middleware Conference},
  year={2021}
}
Datacenter servers are increasingly heterogeneous: from x86 host CPUs, to ARM or RISC-V CPUs in NICs/SSDs, to FPGAs. Previous works have demonstrated that migrating application execution at run-time across heterogeneous-ISA CPUs can yield significant performance and energy gains, with relatively little programmer effort. However, FPGAs have often been overlooked in that context: hardware acceleration using FPGAs involves statically implementing select application functions, which prohibits… 

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