XPoint cache: Scaling existing bus-based coherence protocols for 2D and 3D many-core systems

Abstract

With multi-core processors now mainstream, the shift to many-core processors poses a new set of design challenges. In particular, the scalability of coherence protocols remains a significant challenge. While complex Network-on-Chip interconnect fabrics have been proposed and in some cases implemented, most of industry has slowly evolved existing coherence… (More)
DOI: 10.1145/2370816.2370829

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Cite this paper

@article{Dreslinski2012XPointCS, title={XPoint cache: Scaling existing bus-based coherence protocols for 2D and 3D many-core systems}, author={Ronald G. Dreslinski and Thomas Manville and Korey Sewell and Reetuparna Das and Nathaniel Ross Pinckney and Sudhir Satpathy and David Blaauw and Dennis Sylvester and Trevor N. Mudge}, journal={2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)}, year={2012}, pages={75-85} }