XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference

@article{Conti2018XNORNE,
  title={XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference},
  author={Francesco Conti and Pasquale Davide Schiavone and Luca Benini},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2018},
  volume={37},
  pages={2940-2951}
}
Binary neural networks (BNNs) are promising to deliver accuracy comparable to conventional deep neural networks at a fraction of the cost in terms of memory and energy. [] Key Result We show post-synthesis results in 65- and 22-nm technology for the XNE IP and post-layout results in 22 nm for the full MCU indicating that this system can drop the energy cost per binary operation to 21.6 fJ per operation at 0.4 V, and at the same time is flexible and performant enough to execute state-of-the-art BNN topologies…
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References

SHOWING 1-10 OF 44 REFERENCES

XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks

XNORBIN is presented, a flexible accelerator for binary CNNs with computation tightly coupled to memory for aggressive data reuse supporting even non-trivial network topologies with large feature map volumes.

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically.

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

This work implemented a 65nm 4Kb algorithm-dependent CIM-SRAM unit-macro and in-house binary DNN structure, for cost-aware DNN AI edge processors, and resulted in the first binary-based CIM -SRAM macro with the fastest PS operation, and the highest energy-efficiency among reported CIM macros.

YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration

This paper presents an accelerator optimized for binary-weight CNNs that significantly outperforms the state-of-the-art in terms of energy and area efficiency and removes the need for expensive multiplications, as well as reducing I/O bandwidth and storage.

NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps

A flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios and exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements is proposed.

XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs

A novel process-in-memory architecture to process emerging binary CNN tests in Wide-IO2 DRAMs is presented, which improves CNN test performance by 4× ∼ 11× with small hardware and power overhead.

A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing

Mia Wallace is presented, a 65-nm system-on-chip integrating a near-threshold parallel processor cluster tightly coupled with a CNN accelerator that achieves peak energy efficiency of 108 GMAC/s/W at 0.72 V and peak performance of 14 GMac/s at 1.2 V.

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

FINN, a framework for building fast and flexible FPGA accelerators using a flexible heterogeneous streaming architecture that implements fully connected, convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements is presented.

Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?

The hardware design and synthesis of a purely combinational BNN for ultra-low power near-sensor processing, which features a 10× higher energy efficiency and major opportunities raised by BNN models.

An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS

A mixed-signal binary CNN processor that performs image classification of moderate complexity and employs near-memory computing to achieve a classification energy of 3.8μJ, a 40x improvement over TrueNorth.