Corpus ID: 32937179

X-Propagation Woes : Masking Bugs at RTL and Unnecessary Debug at the Netlist

@inproceedings{Piper2012XPropagationW,
  title={X-Propagation Woes : Masking Bugs at RTL and Unnecessary Debug at the Netlist},
  author={Lisa Piper and Vishnu C. Vimjam},
  year={2012}
}
: This paper presents a complete and practical methodology to comprehensively solve the X problem in RTL design. It begins by reviewing common sources of Xs, and describes how they cause functional bugs as well as unwarranted debug that prolong verification cycles. Solving the X problem helps minimize simulation and synthesis iterations and enables various design analyses (e.g. power analysis), normally performed on netlists, to begin sooner. The pros and cons of various point solutions to this… Expand

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References

SHOWING 1-6 OF 6 REFERENCES
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
TLDR
This work proposes innovative methods to handle don't-care conditions accurately at high-level designs and proposes two novel algorithms based on these methods to minimize the number of registers that need to be initialized at the architecture level. Expand
SystemVerilog Assertions Handbook, 2nd edition for Dynamic and Formal Verification, ISBN 878-0-9705394-8-7 http://SystemVerilog.us
  • 2010
Formal verification enables safe X handling
  • December 16,
  • 2008
An introduction to symbolic simulation
  • EE Times December
  • 2005
Formal Verification Methods 2: Symbolic Simulation
  • Marktoberdorf
  • 2003
The Dangers of Living with an X
  • SNUG Boston,
  • 2003