X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing

@article{Li2010XFillingFS,
  title={X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing},
  author={Jia Li and Qiang Xu and Yu Hu and Xiaowei Li},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2010},
  volume={18},
  pages={1081-1092}
}
Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both shift and capture phases, which can cause circuits' reliability concerns during manufacturing test. This paper proposes a novel X-filling technique, namely “iFill”, to address the above issue, by analyzing the impact of X-bits on… CONTINUE READING