Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

@article{Nirschl2007WriteSF,
  title={Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory},
  author={Thomas Nirschl and J. B. Phipp and T. D. Happ and G. O. BURR and Bahe Rajendran and M.-H. Lee and A. Schrott and Minghui Yang and Matt Breitwisch and C.-F. Chen and E. A. Joseph and Mark C. Lamorey and Roger Cheek and S.-H. Chen and Saleem Zaidi and Simone Raoux and Y. C. Chen and Yuefeng Zhu and R. Bergmann and H.-L. Lung and Christopher Lam},
  journal={2007 IEEE International Electron Devices Meeting},
  year={2007},
  pages={461-464}
}
We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4 bits/cell and a 32 kb memory page at 2 bits/cell are experimentally demonstrated. 
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