Write Assist Scheme to Enhance SRAM Cell Reliability Using Voltage Sensing Technique

@article{Gupta2016WriteAS,
  title={Write Assist Scheme to Enhance SRAM Cell Reliability Using Voltage Sensing Technique},
  author={Rajat Gupta and Vijit Gadi and H. Anirudh Upendar},
  journal={2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)},
  year={2016},
  pages={318-322}
}
Voltage scaling is necessary to minimize power consumption. But the low voltages impede write in static random access memories (SRAMs). Condition is worsened when the periphery voltage is kept lower than the array voltage. Such nature of SRAMs at low voltages makes the use of write assist techniques inevitable. Negative bit line (NBL) technique proves to be the most efficient of all the assist techniques. But a large negative dip on bit line creates reliability issues. To cater for such issues… CONTINUE READING

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