Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism

@article{Amory2007WrapperDF,
  title={Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism},
  author={Alexandre M. Amory and Kees G. W. Goossens and Erik Jan Marinissen and Marcelo Lubaszewski and Fernando Gehm Moraes},
  journal={IET Computers & Digital Techniques},
  year={2007},
  volume={1},
  pages={197-206}
}
A new core test wrapper design approach is proposed which transports streaming test data, for example scan test patterns, into and out of an embedded core exclusively via (some of) its functional data ports. The latter are typically based on standardised protocols such as AXI, DTL, and OCP. The new wrapper design allows a functional interconnect, such as an on-chip bus or network-on-chip (NOC) to transport test data to embedded cores, and hence eliminates the need for a conventional dedicated… CONTINUE READING

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Key Quantitative Results

  • For 672 example cases based on the ITC'02 System-on-Chip (SOC) Test Benchmarks, the new approach in comparison with the conventional approach shows an average wrapper area increase of 14.5%, which is negligible at the SOC level, especially since the dedicated TAM can be eliminated.

Citations

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Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing

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  • 2008
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A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC

  • 2008 17th Asian Test Symposium
  • 2008
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