• DOI:10.1145/3526241.3530368
• Corpus ID: 248366708

Would Magnonic Circuits Outperform CMOS Counterparts?

@article{Mahmoud2022WouldMC,
  title={Would Magnonic Circuits Outperform CMOS Counterparts?},
  author={Abdulqader Nael Mahmoud and Nicoleta Cucu Laurenciu and Frederic Vanderveken and Florin Ciubotaru and Christoph Adelmann and Sorin Dan Cotofana and Said Hamdioui},
  journal={Proceedings of the Great Lakes Symposium on VLSI 2022},
  year={2022}
}

• A. Mahmoud, N. C. Laurenciu, +4 authors S. Hamdioui
• Published 22 April 2022
• Computer Science
• Proceedings of the Great Lakes Symposium on VLSI 2022

In the early stages of a novel technology development, it is difficult to provide a comprehensive assessment of its potential capabilities and impact. Nevertheless, some preliminary estimates can be drawn and are certainly of great interest and in this paper we follow this line of reasoning within the framework of the Spin Wave (SW) based computing paradigm. In particular, we are interested in assessing the technological development horizon that needs to be reached in order to unleash the full SW paradigm potential such that SW circuits can outperform CMOS counterparts in terms of energy consumption. In view of the zero power SWs propagation through ferromagnetic waveguides, the overall SW circuit power consumption is determined by the one associated to SWs generation and sensing by means of transducers. While current antenna based transducers are clearly power hungry recent developments indicate that magneto-electric (ME) cells have a great potential for ultra-low power SW generation and sensing. Given that MEs have been only proposed at the conceptual level and no actual experimental demonstration has been reported we cannot evaluate the impact of their utilization on the SW circuit energy consumption. However, we can perform a reverse engineering alike analysis to determine ME delay and power consumption upper bounds that can place SW circuits in the leading position. To this end, we utilize a 32-bit Brent-Kung Adder (BKA) as discussion vehicle and compute the maximum ME delay and power consumption that could potentially enable a SW implementation able to outperform its 7nm CMOS counterpart. We evaluate different BKA SW implementations that rely on conversion- or normalization-based gate cascading and consider continuous or pulsed SW generation scenarios. Our evaluations indicate that 31nW is the maximum transducer power consumption for which a 32-bit Brent-Kung SW implementation can outperform its 7nm CMOS counterpart in terms of energy consumption.