Worst-case static noise margin criteria for logic circuits and their mathematical equivalence

  title={Worst-case static noise margin criteria for logic circuits and their mathematical equivalence},
  author={Jan Lohstroh and E. Seevinck and J. G. de Groot},
  journal={IEEE Journal of Solid-State Circuits},
Various criteria have been formulated in the past for analytically calculating the worst-case static noise margins of logic circuits. Some of these criteria are based on infinitely long chains of gates, others on flip-flop circuits. It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin. Furthermore, the formal equivalence of four criteria for this worst-case static noise margin is demonstrated. Additionally, a method… CONTINUE READING
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Publications referenced by this paper.
Showing 1-2 of 2 references

Noise margin and noise immunity in logic circuits Static and dynarmc noise margins of logic circuits

IEEE J , Solid - State Circuits • 1979

Temperature behavior of the voltage swings and static noise margins of ‘ ISL and STL

R. M. Pluta
Tech . Dig . , Euro . Solid - State Circuits Conf .

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