Worst-case static noise margin criteria for logic circuits and their mathematical equivalence

@article{Lohstroh1983WorstcaseSN,
  title={Worst-case static noise margin criteria for logic circuits and their mathematical equivalence},
  author={Jan Lohstroh and E. Seevinck and J. G. de Groot},
  journal={IEEE Journal of Solid-State Circuits},
  year={1983},
  volume={18},
  pages={803-807}
}
Various criteria have been formulated in the past for analytically calculating the worst-case static noise margins of logic circuits. Some of these criteria are based on infinitely long chains of gates, others on flip-flop circuits. It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin. Furthermore, the formal equivalence of four criteria for this worst-case static noise margin is demonstrated. Additionally, a method… CONTINUE READING
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IEEE J , Solid - State Circuits • 1979

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