Worst-case noise area prediciton of on-chip power distribution network

Abstract

Clock grid is a mainstream clock network methodology for high performance microprocessor and SOC designs. Clock skew, power usage and robustness to PVT (power, voltage, temperature) are all important metrics for a high quality clock grid design. Tree-driven-grid clock network is a typical clock grid clock network. It includes a clock source, a buffered tree, leaf buffers, a mesh clock grid, local clock buffers, and latches as shown in Fig. 1. For such network, one big challenge is how to connect the leaf level buffers of the global tree to the grid with nonuniform loads under tight slew and skew constraints. The choice of tapping points that connect the leaf buffers to the clock grid are critical to the quality of the clock designs. Good tapping points can minimize the clock skew and reduce power. In this paper, we proposed a new algorithm to select the tapping points to build the global tree as regular and symmetric as possible. From our experimental results, the proposed algorithm can efficiently reduce global clock skew, rising slew, maximum overshoot, reduce power, and avoid local skew violation.

DOI: 10.1145/2633948.2633951

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Cite this paper

@inproceedings{Zhang2014WorstcaseNA, title={Worst-case noise area prediciton of on-chip power distribution network}, author={Xiang Zhang and Jingwei Lu and Yang Liu and Chung-Kuan Cheng}, booktitle={SLIP}, year={2014} }