Worst case delay analysis for memory interference in multicore systems

  title={Worst case delay analysis for memory interference in multicore systems},
  author={Rodolfo Pellizzoni and Andreas Schranzhofer and Jian-Jia Chen and Marco Caccamo and Lothar Thiele},
  journal={2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)},
Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a task's WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival… CONTINUE READING

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