Working with Process Variation Aware Caches

@inproceedings{WorkingWP,
  title={Working with Process Variation Aware Caches},
  author={}
}
    Deep-submicron designs have to take care of process variation effects as it is very difficult to control critical process parameters in deep-submicron technologies. Variations in critical process parameters result in large variations in access latencies of hardware components. This is very severe in the case of memory components as minimum sized transistors… CONTINUE READING