Working with Process Variation Aware Caches

@article{Mutyam2007WorkingWP,
  title={Working with Process Variation Aware Caches},
  author={Madhu Mutyam and Narayanan Vijaykrishnan},
  journal={2007 Design, Automation & Test in Europe Conference & Exhibition},
  year={2007},
  pages={1-6}
}
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware components. This is severe in the case of memory components as minimum sized transistors are used in their design. In this work, by considering on-chip data caches, we study the effect of access latency variations on performance. We discuss performance losses due to the worst-case design, wherein the entire cache operates… CONTINUE READING
Highly Cited
This paper has 29 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 23 extracted citations

LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches

2011 24th Internatioal Conference on VLSI Design • 2011
View 6 Excerpts
Highly Influenced

Reducing performance impact of process variation for data caches

2013 8th International Conference on Electrical and Electronics Engineering (ELECO) • 2013
View 2 Excerpts

Variability-aware memory management for nanoscale computing

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) • 2013
View 1 Excerpt

References

Publications referenced by this paper.

Similar Papers

Loading similar papers…