Within-die process variations: How accurately can they be statistically modeled?

  title={Within-die process variations: How accurately can they be statistically modeled?},
  author={B. Hargreaves and H. Hult and S. Reda},
  journal={2008 Asia and South Pacific Design Automation Conference},
  • B. Hargreaves, H. Hult, S. Reda
  • Published 2008
  • Engineering, Computer Science
  • 2008 Asia and South Pacific Design Automation Conference
  • Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of ICs from their designers' original intent. These deviations reduce the parametric yield and revenues from integrated circuit fabrication. In this paper we provide a complete treatment to the subject of within-die variations. We propose a scan-chain based system, vMeter, to extract within-die variations in an… CONTINUE READING
    55 Citations

    Figures, Tables, and Topics from this paper.

    Die-to-die and within-die fabrication variation of 65nm CMOS technology PMOS transistors
    Analyzing the impact of process variations on parametric measurements: Novel models and applications
    • S. Reda, S. Nassif
    • Engineering, Computer Science
    • 2009 Design, Automation & Test in Europe Conference & Exhibition
    • 2009
    • 49
    • PDF
    REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations
    • 23
    • PDF
    Process variability at the 65nm node and beyond
    • S. Nassif
    • Engineering, Computer Science
    • 2008 IEEE Custom Integrated Circuits Conference
    • 2008
    • 50
    Reliable Integrated Circuits Design and Test at Sub-45nm Technologies
    Process variation aware DRAM design using block based adaptive body biasing algorithm
    • 6
    Accurate Spatial Estimation and Decomposition Techniques for Variability Characterization
    • S. Reda, S. Nassif
    • Mathematics
    • IEEE Transactions on Semiconductor Manufacturing
    • 2010
    • 16
    • PDF
    Process mismatch analysis based on reduced-order models
    • 2
    Computation Reduction for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits
    • 1
    • PDF
    Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits
    • 1


    Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits
    • 55
    • Highly Influential
    • PDF
    Robust Extraction of Spatial Correlation
    • 232
    • Highly Influential
    • PDF
    A General Framework for Spatial Correlation Modeling in VLSI Design
    • F. Liu
    • Mathematics, Computer Science
    • 2007 44th ACM/IEEE Design Automation Conference
    • 2007
    • 102
    • Highly Influential
    • PDF