Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

@article{Dighe2011WithinDieVD,
  title={Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor},
  author={Saurabh Dighe and Sriram R. Vangal and Paolo A. Aseron and Shasi Kumar and Tiju Jacob and Keith A. Bowman and Jason Howard and James W. Tschanz and Vasantha Erraguntla and Nitin Borkar and Vivek De and Shekhar Y. Borkar},
  journal={IEEE Journal of Solid-State Circuits},
  year={2011},
  volume={46},
  pages={184-193}
}
In this paper, we present measured within-die core-to-core Fmax and leakage variation data for an 80-core processor in 65 nm CMOS and 1) populate a parameterized energy/performance model to determine the most energy-efficient operating point for a workload; 2) examine impacts of per-core clock and power gating on optimal dynamic voltage-frequency-core scaling (DVFCS) operating points; and 3) compare improvements in energy efficiency achievable by variation-aware DVFCS and core mapping on Single… CONTINUE READING
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