Wire Topology Optimization for Low Power CMOS

@article{Zuber2009WireTO,
  title={Wire Topology Optimization for Low Power CMOS},
  author={Paul Zuber and Othman Bahlous and Thomas Ilnseher and Michael Ritter and Walter Stechele},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2009},
  volume={17},
  pages={1-11}
}
An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Non-uniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing optimization methodology based on non-uniform spacing is proposed for entire circuits. No area investment is required, since whitespace remaining after detailed routing is exploited. The proposed methodology has been implemented and tapped into an… CONTINUE READING

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