Design of reliable chips with high yield is an extremely challenging task in UDSM technologies. Time to market pressures, which often limit the necessary verification before tape-out, typically are manifested as ramp-to-production problems on “good” designs either in the manufacturing process or in the field. Burn-in process, a reactive measure to ship reliable chips, is not effective for high volume designs. Another cause for concern is hidden failures that go undetected due to incompleteness of test vectors. This session begins with an embedded tutorial that examines a number of “bad things that can happen to good chips” both during manufacturing and in the field. The concept of “design marginality” which can significantly affect manufacturing yield, the proximity to the “cliffs” in chip operation, and test escapes that could cause failures in the field are discussed. Then the panel, from different perspectives on yield and reliability challenges, will describe their own real-world experiences, and discuss how these challenges could be addressed in the manufacturing process, design, and EDA.
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