What is Physical Synthesis

  title={What is Physical Synthesis},
  author={Zhuo Li and Charles J. Alpert},
VLSI technology scaling has caused interconnect delay to increasingly dominate the overall chip performance. A design that satisfies timing constraints after logic synthesis will not necessarily meet timing constraints after place-androute due to wire delays. Physical synthesis has been emerged as a necessary weapon for design closure. It is a core component of modern VLSI design methodologies for ASIC, game chips and high performance microprocessors. 
Crosstalk Effects on Global Interconnects in Multi core Processors
One of the most harmful effects of noise on circuit operation is the degradation of signal integrity causing uncertainty in the signal delay. The uncertainty of the propagation delay of a signal can
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing
A series of techniques that may relieve the problem of routing challenges, and guide the physical design closure system to produce not only easier to route designs, but also better timing quality are discussed.
Automated, inter-macro channel space adjustment and optimization for faster design closure
A tool is introduced for automatic channel space adjustment and an existence of an optimum channel spacing in which a 35% and 124% reduction in turn-around-time is observed with same or better quality of results, when compared to the taped out version of the same.
The ISPD-2011 routability-driven placement contest and benchmark suite
The ISPD-2011 routability-driven placement contest and the associated benchmark suite are described, and a new benchmark suite that is being released in conjunction with the contest is described, which can be used to perform both placement and global routing.


What makes a design difficult to route
This work overviews the complexities with modeling congestion during physical synthesis and discusses how optimizations may be able to provide some relief.
Fast interconnect synthesis with layer assignment
The importance of layer assignment over wire sizing is outlined, and efficient techniques to perform concurrent buffer insertion and layer assignment to fix the electrical and timing problems, while maintaining speed and efficient use of resources are presented.
Techniques for Fast Physical Synthesis
This paper discusses some newer techniques that have been deployed within IBM's physical synthesis tool called PDS that significantly improves throughput and focuses on some of the biggest contributors to runtime, placement, legalization, buffering, and electric correction.
Handbook of Algorithms for Physical Design Automation
Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade.
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment
  • Yifang Liu, Jiang Hu
  • Computer Science
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
  • 2010
The core idea of this approach is joint relaxation and restriction, which employs consistency relaxation and coupled bi-directional solution search, which can lead to about 22% less power dissipation subject to the same timing constraints.
Alpert , Shiyan Hu , Tuhin Muhmud , Stephen T . Quay , and Paul G . Villarrubia , “ Fast interconnect synthesis with layer assignment , ” In
Villarrubia , and Mehmet Yildiz , " Techniques for Fast Physical Synthesis
  • , and Sachin S . Sapatnekar , " Handbook of Algorihms for Physical Design Automation