What is Physical Synthesis

@inproceedings{Li2011WhatIP,
  title={What is Physical Synthesis},
  author={Zhuo Li and Charles J. Alpert},
  year={2011}
}
VLSI technology scaling has caused interconnect delay to increasingly dominate the overall chip performance. A design that satisfies timing constraints after logic synthesis will not necessarily meet timing constraints after place-androute due to wire delays. Physical synthesis has been emerged as a necessary weapon for design closure. It is a core component of modern VLSI design methodologies for ASIC, game chips and high performance microprocessors. 
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References

SHOWING 1-7 OF 7 REFERENCES
What makes a design difficult to route
TLDR
This work overviews the complexities with modeling congestion during physical synthesis and discusses how optimizations may be able to provide some relief.
Fast interconnect synthesis with layer assignment
TLDR
The importance of layer assignment over wire sizing is outlined, and efficient techniques to perform concurrent buffer insertion and layer assignment to fix the electrical and timing problems, while maintaining speed and efficient use of resources are presented.
Techniques for Fast Physical Synthesis
TLDR
This paper discusses some newer techniques that have been deployed within IBM's physical synthesis tool called PDS that significantly improves throughput and focuses on some of the biggest contributors to runtime, placement, legalization, buffering, and electric correction.
Handbook of Algorithms for Physical Design Automation
TLDR
Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade.
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment
  • Yifang Liu, Jiang Hu
  • Computer Science
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
  • 2010
TLDR
The core idea of this approach is joint relaxation and restriction, which employs consistency relaxation and coupled bi-directional solution search, which can lead to about 22% less power dissipation subject to the same timing constraints.
Alpert , Shiyan Hu , Tuhin Muhmud , Stephen T . Quay , and Paul G . Villarrubia , “ Fast interconnect synthesis with layer assignment , ” In
Villarrubia , and Mehmet Yildiz , " Techniques for Fast Physical Synthesis
  • , and Sachin S . Sapatnekar , " Handbook of Algorihms for Physical Design Automation