WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture

Abstract

WaveSync is a network-on-chip architecture for a globally asynchronous locally-synchronous (GALS) design. The WaveSync design facilitates low-latency communication leveraging the source-synchronous clock sent along with the data to time components in the datapath of a downstream router, reducing the number of synchronizations needed. WaveSync accomplishes this by partitioning the router components at each node into different clock domains, each synchronized with one of the orthogonal incoming source-synchronous clocks in a GALS 2D mesh network. The data and clock subsequently propagate through each node/router synchronously until the destination is reached, regardless of the number of hops this may take. As long as the data travels in the path of clock propagation and no congestion is encountered, it will be propagated without latching as if in a long combinatorial path, with both the clock and the data accruing delay at the same rate. The result is that the need for synchronization between the mesochronous nodes and/or the asynchronous control associated with the typical GALS network is completely eliminated. To further reduce the latency overhead of synchronization, for those occasions when synchronization is still required (when a flit takes a turn or arrives at the destination), we propose a novel less-than-one-cycle synchronizer. The proposed WaveSync network outperforms conventional GALS networks by 87--90% in average latency, synthesized using a 45nm CMOS library.

DOI: 10.1145/2647950

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Cite this paper

@article{Yang2014WaveSyncLS, title={WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture}, author={Yoon Seok Yang and Reeshav Kumar and Gwan S. Choi and Paul Gratz}, journal={ACM Trans. Design Autom. Electr. Syst.}, year={2014}, volume={19}, pages={34:1-34:22} }