Wasted dynamic power and correlation to instruction set architecture for CPU throttling

@article{Owahid2018WastedDP,
  title={Wasted dynamic power and correlation to instruction set architecture for CPU throttling},
  author={Abdullah A. Owahid and Eugene John},
  journal={The Journal of Supercomputing},
  year={2018},
  volume={75},
  pages={2436-2454}
}
Reducing dynamic power consumption is one of the major design goals in modern high-performance processor design. Throttling is a mechanism that reduces dynamic power at the expense of reduced throughput. Instruction profiling can identify a set of instructions suitable for fine-grained throttling without significant performance degradation. In this paper, an Electronic Design Automation (EDA) flow was developed to process pipeline trace at an early stage to identify the bottleneck. Using the… CONTINUE READING

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