Wafer-scale integration of analog neural networks

@article{Schemmel2008WaferscaleIO,
  title={Wafer-scale integration of analog neural networks},
  author={J. Schemmel and J. Fieres and K. Meier},
  journal={2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence)},
  year={2008},
  pages={431-438}
}
  • J. Schemmel, J. Fieres, K. Meier
  • Published 2008
  • Computer Science
  • 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence)
  • This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time analog neurons with up to 16 k inputs. A novel interconnection and routing scheme allows the mapping of a multitude of network models derived from biology on the VLSI neural network while maintaining a high resource usage. A single 20 cm wafer contains about 60 million synapses. The implemented neurons are highly accelerated… CONTINUE READING
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