Voltage island aware floorplanning for power and timing optimization

  title={Voltage island aware floorplanning for power and timing optimization},
  author={Wan-Ping Lee and Hung-Yi Liu and Yao-Wen Chang},
Highly Cited
This paper has 109 citations. REVIEW CITATIONS

From This Paper

Topics from this paper.


Publications citing this paper.
Showing 1-10 of 57 extracted citations

SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2012
View 8 Excerpts
Highly Influenced

MSV-Driven Floorplanning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2011
View 7 Excerpts
Highly Influenced

Network flow-based power optimization under timing constraints in MSV-driven floorplanning

2008 IEEE/ACM International Conference on Computer-Aided Design • 2008
View 9 Excerpts
Highly Influenced

Gate movement for timing improvement on row based Dual-VDD designs

2016 17th International Symposium on Quality Electronic Design (ISQED) • 2016
View 2 Excerpts
Highly Influenced

Level shifter planning for timing constrained multi-voltage SoC floorplanning

ACM Great Lakes Symposium on VLSI • 2014
View 4 Excerpts
Highly Influenced

Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) • 2018
View 1 Excerpt

F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2014
View 3 Excerpts

Post-floorplanning power optimization for MSV-driven application specific NoC design

2014 IEEE International Symposium on Circuits and Systems (ISCAS) • 2014
View 1 Excerpt

109 Citations

Citations per Year
Semantic Scholar estimates that this publication has 109 citations based on the available data.

See our FAQ for additional information.