Voltage Controlled Delay Line with PFD for Delay Locked Loop in CMOS 90nm Technology

  • I I Patel, IIPriyesh P. Gandhi, IIINilesh D. Patel, IVJaimini Prajapati
  • Published 2014

Abstract

I. Introduction In this high-speed generation and high-integration density systems, the synchronous adjustment between the different systems is very important. Asynchronous clock which were caused by the phase error would be a serious threat to the correctness of the operation of the whole circuit. The Phase Locked Loop (PLL) and Delay-Locked Loop (DLL) are… (More)

Topics

10 Figures and Tables

Cite this paper

@inproceedings{Patel2014VoltageCD, title={Voltage Controlled Delay Line with PFD for Delay Locked Loop in CMOS 90nm Technology}, author={I I Patel and IIPriyesh P. Gandhi and IIINilesh D. Patel and IVJaimini Prajapati}, year={2014} }