Corpus ID: 55020740

Void Reduction during Low Pressure Lamination of Electronic Assemblies

  title={Void Reduction during Low Pressure Lamination of Electronic Assemblies},
  author={David C. Timpe and A. Cloud},
  • David C. Timpe, A. Cloud
  • Published 2006
  • Materials Science
  • Void content at the interface of the bonding adhesive and rigid substrate of an electronic assembly can affect critical performance metrics such as thermal transfer, bond strength, and stress decoupling which can ultimately lead to poor device reliability. In this paper, the contribution of substrate size and lamination method on void content is investigated. It is shown that void content increases with increasing air escape path length. Since the voids are pockets of air entrapped during… CONTINUE READING
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