Vlsi Architecture for Optimized Low Power Digit Serial Fir Filter with Fpga

Abstract

\ Abstract: In the last two decades, many efficient algorithms and architectures have been introduced for the design of low power FIR Filter which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial design that offers alternative low complexity since digit-serial… (More)

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Cite this paper

@inproceedings{Pusegaonkar2014VlsiAF, title={Vlsi Architecture for Optimized Low Power Digit Serial Fir Filter with Fpga}, author={Samidha Shirish Pusegaonkar}, year={2014} }