Vijaya Bhaskar M, Suparshya Babu Sukhavasi, Susrutha


Self-resetting logic is a commonly used piece of circuitry that can be found in use with memory arrays as word line drivers. Self resetting logic implemented in dynamic logic families have been proposed as viable clock less alternatives. While these circuits can produce excellent performance, they display serious limitations in terms of area cost and power consumption. A middle of the road alternative, which can provide a good performance and avoid the limitations see in dynamic self resetting circuits, would be to implement self resetting behavior in static circuits. This alterative has been introduced recently as self resetting logic. The dynamic circuits are becoming increasingly popular because of the speed advantage over static CMOS logic circuits; hence they are widely used today in high performance and low power circuits. This paper says that by using this self resetting logic the low power VLSI circuits can be designed efficiently for counters. Keywords— High speed, VLSI, Self-resetting logic (SRL), topologies, power dissipation

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@inproceedings{SUKHAVASI2012VijayaBM, title={Vijaya Bhaskar M, Suparshya Babu Sukhavasi, Susrutha}, author={BABU SUKHAVASI and G. Vijaya Santhi and SWAROOP VEMANA and V. Bhaskar and Suparshya Babu Sukhavasi and Susrutha Babu Sukhavasi}, year={2012} }