View-Based Axiomatic Reasoning for PSO (Extended Version)
@article{Bargmann2023ViewBasedAR, title={View-Based Axiomatic Reasoning for PSO (Extended Version)}, author={Lara Bargmann and Heike Wehrheim}, journal={ArXiv}, year={2023}, volume={abs/2301.07967} }
. Weak memory models describe the semantics of concurrent programs on modern multi-core architectures. Reasoning techniques for concurrent programs, like Owicki-Gries-style proof calculi, have to be based on such a semantics, and hence need to be freshly developed for every new memory model. Recently, a more uniform approach to reasoning has been proposed which builds correctness proofs on the basis of a number of core axioms . This allows to prove program correctness independent of memory…
37 References
Unifying Operational Weak Memory Verification: An Axiomatic Approach
- Computer ScienceACM Trans. Comput. Log.
- 2022
It is shown that it is possible to prove correctness of a program with respect to a particular axiom scheme, and it is shown to suffice for any memory model that satisfies the axioms.
Owicki-Gries Reasoning for C11 RAR
- Computer ScienceECOOP
- 2020
A new proof calculus for the C11 RAR memory model (a fragment of C11 with both relaxed and release-acquire accesses) that allows all Owicki-Gries proof rules for compound statements, including non-interference, to remain unchanged is developed.
Integrating Owicki–Gries for C11-Style Memory Models into Isabelle/HOL
- Computer ScienceJ. Autom. Reason.
- 2022
This paper introduces the first deductive verification environment in Isabelle/HOL for C11-like weak memory programs, built on the Nipkow and Nieto’s encoding of Owicki–Gries in the Isabelle theorem prover.
A promising semantics for relaxed-memory concurrency
- Computer SciencePOPL
- 2017
The first relaxed memory model that accounts for a broad spectrum of features from the C++11 concurrency model, is implementable, and defines the semantics of racy programs without relying on undefined behaviors, which is a prerequisite for applicability to type-safe languages like Java is proposed.
View-Based Owicki-Gries Reasoning for Persistent x86-TSO (Extended Version)
- Computer ScienceESOP
- 2022
Pierogi is a program logic for reasoning about x86 code that uses low-level operations such as memory accesses and fences, as well as persistency primitives such as flushes, and is mechanised in the Isabelle/HOL proof assistant.
Strong Logic for Weak Memory: Reasoning About Release-Acquire Consistency in Iris
- Computer ScienceECOOP
- 2017
The first foundationally verified framework for proving programs correct under C11's weak-memory semantics is provided, providing a novel operational characterization of RA+NA, the fragment of C11 containing RA accesses and "non-atomic" accesses.
What’s Decidable About Causally Consistent Shared Memory?
- Computer ScienceACM Trans. Program. Lang. Syst.
- 2022
This article establishes the decidability of safety verification for (finite-state) concurrent programs running under causally consistent shared memories under Release/Acquire, and develops an equivalent “lossy” operational semantics, whose states track possible futures, rather than more standard semantics that record the history of the execution.
Stateless model checking for TSO and PSO
- Computer ScienceActa Informatica
- 2016
The basis for the technique is a novel representation of executions under TSO and PSO, called chronological traces, which reduces the verification effort for relaxed memory models to be almost that for the standard model of sequential consistency.
Verifying C11 programs operationally
- Computer SciencePPoPP
- 2019
An operational semantics for a release-acquire fragment of the C11 memory model with relaxed accesses is developed, which relies on a per-thread notion of observability, which allows one to reason about a weak memory C11 program in program order.
The semantics of x86-CC multiprocessor machine code
- Computer SciencePOPL '09
- 2009
This work develops a rigorous and accurate semantics for x86 multiprocessor programs, from instruction decoding to relaxed memory model, mechanised in HOL, and contrast the x86 model with some aspects of Power and ARM behaviour.