Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors

@article{Zhang2005VictimRM,
  title={Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors},
  author={Michael Zhang and Krste Asanovic},
  journal={32nd International Symposium on Computer Architecture (ISCA'05)},
  year={2005},
  pages={336-345}
}
In this paper, we consider tiled chip multiprocessors (CMP) where each tile contains a slice of the total on-chip L2 cache storage and tiles are connected by an on-chip network. The L2 slices can be managed using two basic schemes: 1) each slice is treated as a private L2 cache for the tile 2) all slices are treated as a single large L2 cache shared by all tiles. Private L2 caches provide the lowest hit latency but reduce the total effective cache capacity, as each tile creates local copies of… CONTINUE READING
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