Very-Low-Voltage Testing for Weak CMOS Logic ICs

  title={Very-Low-Voltage Testing for Weak CMOS Logic ICs},
  author={Hong Hao and Edward J. McCluskey},
In this paper we propose a very-low-voltage (VLV) testing technique for CMOS logic ICs. Voltage dependence of CMOS logic circuit operation in the presence of resistive shorts and hot carrier damage is studied. It is shown that at certain much-lower-thannormal power supply voltage, weak CMOS logic ICs due to the presence of these flaws can be forced to malfunction while truly good ICs continue to function. Very-lowvoltage testing also detects pattern dependent faults caused by resistive shorts… CONTINUE READING
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