Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

@article{Yang2008VerticalSF,
  title={Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET},
  author={Bin Yang and K. Buddharaju and S. H. G. Teo and Navab Singh and G. Q. Lo and D. L. Kwong},
  journal={IEEE Electron Device Letters},
  year={2008},
  volume={29},
  pages={791-794}
}
This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large… CONTINUE READING
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Showing 1-10 of 22 references

High - performance fully depleted silicon nanowire ( diameter ≤ 5 nm ) gate - all - around CMOS devices Turning the world vertical : MOSFETs with current flow perpendicular to the wafer surface

  • K. Sunouchi H. Takato, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, F. Masuoka
  • Appl . Phys .
  • 2007

Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface

  • J. Moers
  • Appl. Phys., vol. A87, no. 3, pp. 531– 537, Jun…
  • 2007
1 Excerpt

A novel 50 nm vertical MOSFET with a dielectric pocket

  • S. K. Jayanarayanan, S. Dey, J. P. Donnelly, S. K. Banerjee
  • Solid State Electron., vol. 50, no. 5, pp. 897…
  • 2006

Fabrication of a verticalchannel double-gate metal–oxide–semiconductor field-effect transistor using a neutral beam etching

  • K. Endo, S. Noda, +11 authors E. Suzuki
  • Jpn. J. Appl. Phys., vol. 45, no. 10, pp. L279…
  • 2006

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