Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

  title={Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET},
  author={Bin Yang and K. Buddharaju and S. H. G. Teo and Navab Singh and G. Q. Lo and D. L. Kwong},
  journal={IEEE Electron Device Letters},
This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large… CONTINUE READING
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