Verilog Implementation Of Da Based Dct With High Accuracy Error-Compensated Adder Tree


In brief, by operating the shifting and addition in parallel, an error-compensated addertree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet… (More)

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