Verilog Implementation Of Da Based Dct With High Accuracy Error-Compensated Adder Tree

Abstract

In brief, by operating the shifting and addition in parallel, an error-compensated addertree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet… (More)

4 Figures and Tables

Topics

  • Presentations referencing similar topics