Verifying a self-timed division chip

@inproceedings{OnoTesfaye1997VerifyingAS,
  title={Verifying a self-timed division chip},
  author={Tarik Ono-Tesfaye},
  year={1997}
}
The formal verification of asynchronous circuits is challenging, because they often have non-deterministic t iming relations between circuit components. Th i s thesis presents a formal proof strategy for verifying the correctness of a dual-rai l , asynchronous divider chip. For that purpose, this thesis wi l l extend t iming verification techniques that were originally developed for combinat ional logic to apply to dualrai l , self-timed designs. The proof strategy is refinement based and… CONTINUE READING

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