Verifying Parallel Loops with Separation Logic

@inproceedings{Blom2014VerifyingPL,
  title={Verifying Parallel Loops with Separation Logic},
  author={Stefan Blom and Saeed Darabi and Marieke Huisman},
  booktitle={PLACES},
  year={2014}
}
This paper proposes a technique to specify and verify whether a loop can be parallelised. Our approach can be used as an additional step in a parallelising compiler to verify user annotations about loop dependences. Essentially, our technique requires each loop iteration to be specified with the locations it will read and write. From the loop iteration specifications, the loop (in)dependences can be derived. Moreover, the loop iteration specifications also reveal where synchronisation is needed… 

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