Verification of parameterized hierarchical state machines using action language verifier

@article{YavuzKahveci2005VerificationOP,
  title={Verification of parameterized hierarchical state machines using action language verifier},
  author={Tuba Yavuz-Kahveci and Tevfik Bultan},
  journal={Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05.},
  year={2005},
  pages={79-88}
}
Action language verifier (ALV) is an infinite-state symbolic model checker. ALV can verify (or falsify, by generating counter-examples) temporal logic properties of systems that can be modeled using a combination of Boolean logic and linear arithmetic expressions on Boolean, enumerated and (possibly unbounded) integer variables and parameterized integer constants. In this paper, we apply ALV to the verification of parameterized hierarchical state machine specifications. We extend the standard… CONTINUE READING