Verification of UML Statechart Models of Embedded Systems

@inproceedings{Darvas2002VerificationOU,
  title={Verification of UML Statechart Models of Embedded Systems},
  author={{\'A}d{\'a}m Darvas and Istv{\'a}n Majzik and Bal{\'a}zs Beny{\'o}},
  year={2002}
}
The test and verification are essential phases of any system development. With the enlargement of the size and complexity of the system under development the importance of these tasks increases. Traditionally the system development is divided into DQDO\VLVV GHVLJQ and LPSOHPHQWDWLRQ phases regardless of the development process applied (Fig. 1). The system development process is typically accompanied by the occurrence of design and implementation faults. To avoid these faults the implementation… CONTINUE READING

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