Verification of STM on relaxed memory models


Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort. However, in a realistic setting, processors use relaxed memory models to optimize hardware performance. Moreover, the atomicity of operations depends on the… (More)
DOI: 10.1007/s10703-011-0131-3

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