Verification of RTL generated from scheduled behavior in a high-level synthesis flow

@article{Ashar1998VerificationOR,
  title={Verification of RTL generated from scheduled behavior in a high-level synthesis flow},
  author={Pranav Ashar and Subhrajit Bhattacharya and Anand Raghunathan and Akira Mukaiyama},
  journal={1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)},
  year={1998},
  pages={517-524}
}
We propose a complete procedure for verifying register transfer logic against its scheduled behavior in a high level synthesis environment. Our proposal advances the state of the art because it is the first such verification procedure that is both complete and practical. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high level synthesis-performed manually or by means of high level synthesis software-proceeds from the… CONTINUE READING
Highly Cited
This paper has 33 citations. REVIEW CITATIONS
22 Citations
1 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 22 extracted citations

References

Publications referenced by this paper.

Similar Papers

Loading similar papers…