Verification of Loop Parallelisations

@inproceedings{Blom2015VerificationOL,
  title={Verification of Loop Parallelisations},
  author={Stefan Blom and Saeed Darabi and Marieke Huisman},
  booktitle={FASE},
  year={2015}
}
Writing correct parallel programs becomes more and more difficult as the complexity and heterogeneity of processors increase. This issue is addressed by parallelising compilers. Various compiler directives can be used to tell these compilers where to parallelise. This paper addresses the correctness of such compiler directives for loop parallelisation. Specifically, we propose a technique based on separation logic to verify whether a loop can be parallelised. Our approach requires each loop… CONTINUE READING