Verification of Building Blocks for Asynchronous Circuits

@inproceedings{Verbeek2013VerificationOB,
  title={Verification of Building Blocks for Asynchronous Circuits},
  author={Freek Verbeek and Julien Schmaltz},
  booktitle={ACL2},
  year={2013}
}
Scalable formal verification constitutes an important challenge for the design of asynchronous circuits. Deadlock freedom is a property that is desired but hard to verify. It is an emergent property that has to be verified monolithically. We present our approach to using ACL2 to verify necessary and sufficient conditions over asynchronous delay-insensitive primitives. These conditions are used to derive SAT/SMT instances from circuits built out of these primitives. These SAT/SMT instances help… 

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