# Verification of Building Blocks for Asynchronous Circuits

@inproceedings{Verbeek2013VerificationOB, title={Verification of Building Blocks for Asynchronous Circuits}, author={Freek Verbeek and Julien Schmaltz}, booktitle={ACL2}, year={2013} }

Scalable formal verification constitutes an important challenge for the design of asynchronous circuits. Deadlock freedom is a property that is desired but hard to verify. It is an emergent property that has to be verified monolithically. We present our approach to using ACL2 to verify necessary and sufficient conditions over asynchronous delay-insensitive primitives. These conditions are used to derive SAT/SMT instances from circuits built out of these primitives. These SAT/SMT instances help…

## 8 Citations

A Framework for Asynchronous Circuit Modeling and Verification in ACL2

- Computer ScienceHaifa Verification Conference
- 2017

This work applies a link-joint paradigm to model asynchronous circuits and applies a hierarchical verification approach to support scalability, and imposes design restrictions to prevent communication between a module M and other modules while computations are still taking place that are internal to M.

Verifying Timed, Asynchronous Circuits using ACL2

- Computer Science2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
- 2019

This paper models a circuit as a trace-recognizer: a trace is a sequence of states where a state is a mapping from hierarchical signal names to values and transition times, and naturally models non-determinism and continuous quantities such as time.

A Hierarchical Approach to Self-Timed Circuit Verification

- Computer Science2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
- 2019

This paper illustrates this extension to parameterized circuit families that may have loops and non-deterministic outputs with iterative self-timed circuits that calculate the greatest common divisor of two natural numbers and with circuits that combine both of these.

Equivalence verification for NULL Convention Logic (NCL) circuits

- Computer Science2014 IEEE 32nd International Conference on Computer Design (ICCD)
- 2014

The methodology includes a procedure that computes the reachable states of NCL sequential circuits and a refinement mapping function that can be used to map NCL circuit states onto synchronous circuit states.

An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits

- Computer Science2019 IEEE International Symposium on Circuits and Systems (ISCAS)
- 2019

This paper proposes a unified formal verification scheme for combinational as well as sequential SCL circuits, based on equivalence checking, which verifies both safety and liveness.

Formal modeling and verification for pre-charge half buffer gates and circuits

- Computer Science2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
- 2017

This work model gates as transition systems and provide correctness property templates that capture safety and liveness in PCHB gates and circuits and demonstrate the methodology using several circuits.

FORMAL VERIFICATION METHODOLOGY FOR ASYNCHRONOUS SLEEP CONVENTION LOGIC CIRCUITS BASED ON EQUIVALENCE VERIFICATION

- Computer Science
- 2019

Data-Loop-Free Self-Timed Circuit Verification

- Computer Science2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
- 2018

This paper uses the DE system, a formal hardware description language built using the ACL2 theorem-proving system, to specify and verify finite-state-machine representations of self-timed circuit designs and applies a link-joint paradigm to model self- Timed circuits as networks of computations that communicate with each other with protocols.

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