Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing

@article{Alioto2015VariationsIN,
  title={Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing},
  author={Massimo Alioto and Elio Consoli and Gaetano Palumbo},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2015},
  volume={62},
  pages={2035-2043}
}
In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops (FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT), as well as the clock network (clock slope variations). For… CONTINUE READING