Variation-tolerant and low-power clock network design for 3D ICs

@article{Zhao2011VariationtolerantAL,
  title={Variation-tolerant and low-power clock network design for 3D ICs},
  author={Xin Zhao and Saibal Mukhopadhyay and Sung Kyu Lim},
  journal={2011 IEEE 61st Electronic Components and Technology Conference (ECTC)},
  year={2011},
  pages={2007-2014}
}
This paper studies the random characteristics of through-silicon-via (TSV)-based 3D clock networks, taking into ac­count both die-to-die and within-die process variations in clock buffers, interconnects, and TSVs. We investigate many design parameters which may cause clock skew variation, including the TSV RC parasitics, the TSV count, the stack die number, and the range of variations. Key insights are as follows: 1) under the circumstances of random uncorrelated TSV variation with no TSV… CONTINUE READING
10 Citations
16 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 10 extracted citations

References

Publications referenced by this paper.
Showing 1-10 of 16 references

Similar Papers

Loading similar papers…