Variation-tolerant Design Using Residue Number System

  title={Variation-tolerant Design Using Residue Number System},
  author={Ioannis Kouretas and Vassilis Paliouras},
  journal={2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools},
Abstract—In this paper the use of residue arithmetic is proposed as a technique to reduce delay variation in adders. It is found that the use of residue arithmetic offers significant delay variation reduction when compared to adders of the literature. Therefore this technique can be used to control variance of critical paths delay and efficiently meet… CONTINUE READING