Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs

@article{Wang2005VariableTP,
  title={Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs},
  author={Hua Wang and Miguel Corbalan and Antonis Papanikolaou and Francky Catthoor and Wim Dehaene},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2005},
  volume={13},
  pages={1127-1135}
}
This paper presents a novel formalized technique for variable tapered buffer design achieving Pareto optimal energy-delay tradeoffs. Our main focus lies on the drivers typically found in embedded SRAMs. Much work has been done for variable tapered buffer design explicitly targeting energy (and/or area) tradeoffs for a given target delay. In contrast, the formalized techniques presented here are capable of providing all existing Pareto configurations achieving optimal energy/delay tradeoffs, and… CONTINUE READING
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